For faster turnaround of ROM's, there is a need to program them as late in the fabrication sequence as possible, so that few (if any) process steps separate the unprogrammed chip from shipment.
Generally, two types of late programming are employed, post-poly (polycrystalline silicon) and post-metal. Both techniques usually rely on high-energy ion implantation, of boron for example, to increase the boron doping concentration in the channel region beneath the gate so as to render the gate threshold voltage of selected transistors sufficiently high so that they will not turn on. The configuration of the selected transistors corresponds to the ROM program code.
The aforementioned ion implantation must be done at a sufficiently high energy to put the peak of the as-implanted profile under the oxide/channel interface, which means that the boron must get through the gate oxide, poly gate, and whatever films are, at that point, on top of the polysilicon. There are three reasons why the peak must get that far:
a. The as-implanted distribution drops off from its peak concentration so rapidly that an impracticably longer implantation time would be required to bring a far-side tail concentration up to the needed value.
b. It is undesirable, with the doses involved, to leave the majority of the dopant back in the gate oxide and/or poly.
c. Small variations in thicknesses of barrier films cause larger variations in concentration of the tail distribution than near the peak (center).
In post-poly programming, the wafers have patterned poly gates, a mask is used to open up selected transistors, and the high energy ion implantation is performed. In the subsequent process steps, the implanted boron sees high enough temperatures to effect nearly 100 percent substitution and lattice annealing, but these process steps add to the turn-around time.
Commonly-owned U.S. Pat. No. 4,356,042 (Gedaly, 1982) and U.S. Pat. Nos. 4,333,164 (Orikabe et al, 1982) and 4,208,727 (Redwine et al., 1980) are typical of the post-poly techniques.
In post-metal programming, the wafers have patterned metal interconnections, a mask is used to open up selected transistors, the metal-to-poly dielectric is etched back to a small thickness over these transistors, and the high-energy ion implantation is performed. The highest subsequent temperature seen by the wafer is 425.degree. C., which is not enough to activate the boron beyond its expected 25 percent (or so) as-implemented substitutional percentage, and, in fact, may deactivate some of the already substituted boron. Consequently, the dose used is five to ten times higher than in the post-poly programming case, and results in a rather wide threshold range and high degree of unannealed damage. The advantage, of course, is that only a minimal amount of processing remains to be done after programming. The yield, however, is historically and understandably lower than in the post-poly case.
U.S. Pat. No. 4,390,971 (Kuo, 1983) describes a typical post-metal programming technique. The ROM array is programmed by first depositing the post-metal-oxide or protective oxide layer 21 over the entire slice, then patterning it by a photoresist mask and etch sequence using a unique mask which defines the ROM code. An aperture 22 is defined over each cell 10 to be programmed as a "0", and each cell 10 to be a "1" is left covered. The slice is then subjected to a boron implant of about 180 Kev to a dosage of about 10.sup.13 ions per sq. cm. The energy level and dosage are dependent upon the thickness of the oxide layer 19 and the polysilicon gates 11, as well as the change in threshold desired. At this level, the ion implant penetrates the polycrystalline silicon gate 11 and gate oxide 19 to create an implanted region 23 in the channel area. This implant raises the threshold voltage above 5 V. Since the part operates on a supply voltage Vdd of 5 V., the full logic 1 level will not turn on the transistor. The transistors covered by the oxide 21 will not be implanted so will retain the usual threshold voltage of about 0.8 V. U.S. Pat. No. 4,198,693 (Kuo, 1980) describes a similar process for a VMOS ROM. Somewhat less voltage is required when the metal over the gates has been removed, as discussed in U.S. Pat. No. 4,342,100 (Kuo, 1982). Even less voltage may be required when the implant is performed prior to metalization (forming contacts and interconnects), as described in U.S. Pat. Nos. 4,364,167 (Donley, 1982) and 4,295,209 (Donley, 1981).
In both post-poly and post-metal boron implant type late programming, the high-energy ion implantation can have yield degrading effects.